module disp_scan #(
    parameter base_CLK = 50_000_000,
    parameter STOP = 500_000,
    //显示的数据
    parameter NUM0 = 2,
    parameter NUM1 = 0,
    parameter NUM2 = 2,
    parameter NUM3 = 3,
    parameter NUM4 = 0,
    parameter NUM5 = 4,
    parameter NUM6 = 2,
    parameter NUM7 = 5
) (
    input            CLK,
    input      [7:0] KEY,
    output reg [7:0] SEG,
    output reg [7:0] WORD_SEL
);

  reg [ 2:0] CNT;
  reg [ 3:0] DATA;
  reg [24:0] cnt_blink;
  reg        flag_blink;
  initial begin
    flag_blink <= 0;
  end
  always @(CNT) begin
    case (CNT)
      3'd0: begin
        WORD_SEL <= 8'b00000001;
        DATA     <= NUM7;
      end
      3'd1: begin
        WORD_SEL <= 8'b00000010;
        DATA     <= NUM6;
      end
      3'd2: begin
        WORD_SEL <= 8'b00000100;
        DATA     <= NUM5;
      end
      3'd3: begin
        WORD_SEL <= 8'b00001000;
        DATA     <= NUM4;
      end
      3'd4: begin
        WORD_SEL <= 8'b00010000;
        DATA     <= NUM3;
      end
      3'd5: begin
        WORD_SEL <= 8'b00100000;
        DATA     <= NUM2;
      end
      3'd6: begin
        WORD_SEL <= 8'b01000000;
        DATA     <= NUM1;
      end
      3'd7: begin
        WORD_SEL <= 8'b10000000;
        DATA     <= NUM0;
      end
      default: begin
        WORD_SEL <= 8'b00000000;
        DATA     <= 0;
      end
    endcase
  end

  always @(posedge CLK) begin
    case (KEY)
      8'b00000000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00000001: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd0 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00000010: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd1 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00000100: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd2 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00001000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd3 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00010000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd4 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b00100000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd5 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b01000000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd6 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
      8'b10000000: begin
        if (CNT == 3'd7) begin
          CNT <= 3'd0;
        end else if (CNT == 3'd7 && flag_blink) begin
          CNT <= CNT + 2;
        end else begin
          CNT <= CNT + 1;
        end
      end
    endcase
  end
  always @(posedge CLK) begin

  end
  always @(DATA) begin
    case (DATA)
      4'b0000: SEG <= 8'b11000000;  // C0 0
      4'b0001: SEG <= 8'b11111001;  // F9 1
      4'b0010: SEG <= 8'b10100100;  // A4 2
      4'b0011: SEG <= 8'b10110000;  // B0 3
      4'b0100: SEG <= 8'b10011001;  // 99 4
      4'b0101: SEG <= 8'b10010010;  // 92 5
      4'b0110: SEG <= 8'b10000010;  // 82 6
      4'b0111: SEG <= 8'b11111000;  // F8 7
      4'b1000: SEG <= 8'b10000000;  // 80 8
      4'b1001: SEG <= 8'b10010000;  // 90 9
      4'b1010: SEG <= 8'b10001000;  // 88 A
      4'b1011: SEG <= 8'b10000011;  // 83 B
      4'b1100: SEG <= 8'b11000110;  // C6 C
      4'b1101: SEG <= 8'b10100001;  // D1 D
      4'b1110: SEG <= 8'b10000110;  // 86 E
      4'b1111: SEG <= 8'b10001110;  // 8E F
      default: SEG <= 8'b00000000;
    endcase
  end
  //一个简单的定时器
  always @(posedge CLK) begin
    cnt_blink <= cnt_blink + 1;  // 每个时钟周期计数器都要递增
    if (cnt_blink == STOP) begin  // 每隔一段时间，将数据寄存器的值取反，从而实现闪烁效果
      flag_blink <= ~flag_blink;
    end
  end
endmodule
